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11 years ago @ FPGA Simulation - SystemVerilog Code Exa... · 0 replies · +1 points

Hi Ram,

I answered your question on this page: http://www.fpgasimulation.com/?page_id=2

Ray

11 years ago @ FPGA Simulation - About Us · 0 replies · +1 points

Hi Ram,

There are two ways to do this with SystemVerilog:

1. You can hierarchically reference the result (top.dut.tinyalu.result)

2. You can use a bind command to "instantiate" a monitoring module in the hierarchy.

If you had a module such as

monitor_result monitor_result_i (result);

And if your tinyalu were in top.dut.

you could do

bind top.dut monitor_result monitor_result_i(result)

Both of these solutions do not require you to touch the DUT code.

VHDL 2008 added hierarchical references to VHDL.

11 years ago @ FPGA Simulation - SystemVerilog Code Exa... · 0 replies · +1 points

I believe he's talking about FPGA SIMULATION (link to the right).

12 years ago @ FPGA Simulation - SystemVerilog Code Exa... · 0 replies · +1 points

Hi Sudipta,

When you say "showing 2 error" what do you mean?

Ray

12 years ago @ FPGA Simulation - FPGA Simulation Errata · 0 replies · +1 points

Hi Liu,

I have posted a solution to the IUS problem: http://www.fpgasimulation.com/?page_id=155

12 years ago @ FPGA Simulation - FPGA Simulation Errata · 0 replies · +1 points

Hi Liu,

You're the second person to mention this problem with IUS. There is probably a very ugly way to do this. Let me give it a little thought. I suspect that you can create a variable inside the module that holds the TLM fifo and then use Verilog hierarchical references to set the variable to the TLM fifo.

Also, be sure to tell your Cadence FAE that this has made a Mentor FAE very happy. That should motivate them to fix it faster :-)

Ray

12 years ago @ FPGA Simulation - FPGA Simulation Errata · 0 replies · +1 points

Hi Liu,

I'm not certain what you mean in your message. Do you mean the report looks different?
I wonder if OVM has changed since then.

Ray

13 years ago @ Naked Security - Death by PowerPoint? K... · 0 replies · +1 points

May I snigger now? The headline is just too funny.

13 years ago @ FPGA Simulation - More Lectures from FPG... · 0 replies · +1 points

Hi Aiken,

I've uploaded an example to the SystemVerilog Code Examples page. You can see the tab to the examples page at the top of this page.

14 years ago @ FPGA Simulation - FPGA Simulation Errata · 0 replies · +1 points

Wow. You're right. There's an errata on the errata. How recursive!

I've fixed it.

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